Electrically erasable and programmable memory devices having arrays of flash memory cells are found in a wide variety of electrical devices. A flash memory cell, also known as a floating gate transistor memory cell, is similar to a field effect transistor, having a source region and a drain region that is spaced apart from the source region to form an intermediate channel region. A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the channel region by a layer of gate oxide. A control gate is fabricated over the floating gate, and it can also be made of doped polysilicon. The control gate is electrically separated from the floating gate by a dielectric layer. Thus, the floating gate is “floating’ in the sense that it is insulated from the channel, the control gate and all other components of the flash memory cell.
A flash memory cell is programmed by storing charge on the floating gate. The charge thereafter remains on the gate for an indefinite period even after power has been removed from the flash memory device. Flash memory devices are therefore non-volatile. Charge is stored on the floating gate by applying appropriate voltages to the control gate and the drain or source. For example, a negative charge can be placed on the floating gate by grounding the source while applying a sufficiently large positive voltage to the control gate to attract electrons, which tunnel through the gate oxide to the floating gate from the channel region. The voltage applied to the control gate, called a programming voltage, determines the amount of charge residing on the floating gate after programming.
A flash memory cell can be read by applying a positive control gate to source voltage having a magnitude greater than a threshold voltage. The amount of charge stored on the flash memory cell determines the magnitude of the threshold voltage that must be applied to the control gate to allow the flash memory cell to conduct current between the source and the drain. As negative charge is added to the floating gate, the threshold voltage of the flash memory cell increases. During a read operation, a read voltage is applied to the control gate that is large enough to render the cell conductive if no charge is stored on the floating gate, but not large enough to render the cell conductive if charge is stored on the floating gate. During the read operation, the source is coupled to ground, and a positive voltage is applied through a suitable impedance to the drain, which is used as the output terminal of the cell. Therefore, if the floating gate of the flash memory cell is charged, the drain will remain at the positive voltage. If the floating gate of the flash memory cell is not charged, the cell will ground the drain.
Before a flash memory cell can be programmed, it must be erased by removing charge from the floating gate. The cell can be erased by applying a gate-to-source voltage to the cell that has a polarity opposite that used for programming. Specifically, the control gate is grounded, and a large positive voltage is applied to the source to cause the electrons to tunnel through the gate oxide and deplete the charge from the floating gate. In another approach, a relatively large negative voltage is applied to the control gate, and a positive voltage, such as a supply voltage, is applied to the source region.
A typical flash memory device includes a memory array containing a large number of flash memory cells arranged in rows and columns. Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic flash memory cell configuration for each is arranged. FIG. 1 illustrates a typical NAND flash memory array 10 of conventional design. The array 10 is comprised of a large number of flash memory cells, collectively indicated by reference numeral 14. The array of flash memory cells 14 is typically divided into a number of blocks, one of which is shown in FIG. 1. Each block includes a number of rows, which, in the example shown in FIG. 1, includes 32 rows. The cells 14 in the same row have their control gates coupled to a common word select line 30, each of which receives a respective word line signal WL0-WL31. The cells 14 in the same column having their sources and drains connected to each other in series. Thus all of the memory cells 14 in the same column of each block are typically connected in series with each other. The drain of the upper flash memory cell 14 in the block is coupled to a bit line 20 through a first select gate transistor 24. The conductive state of the transistors 24 in each block are controlled by a source gate SG(D) signal. Each of the bit lines 20 output a respective bit line signal BL1-BLN indicative of the data bit stored in the respective column of the array 10. The bit lines 20 extend through multiple blocks to respective sense amplifiers (not shown). The source of the lower flash memory cell 14 in the block is coupled to a source line 26 through a second select gate transistor 28. The conductive state of the transistors 28 in each block are controlled by a source gate SG(S) signal. The source line 26 receives a signal SL having various magnitudes depending upon whether the memory cells 14 are being programmed, read or erased.
A read operation is performed on a row-by-row basis. When a read operation is to be performed for a selected block, the source line 26 is coupled to ground, and the select gate transistors 24, 28 for that block are turned ON responsive to high SG(D) and SG(S) signals. Also, the bit line 20 for each column is precharged to the supply voltage VCC. Finally, a read voltage is applied to a word select line 30 for the selected row, thereby applying the read voltage to the control gates of all of the flash memory cells 14 in that row. As explained above, the magnitude of the read voltage is sufficient to turn ON all flash memory cells 14 that do not have a charged floating gate, but insufficient to turn ON all cells that have a charged floating gate. A voltage having a higher magnitude is applied to the word select lines 30 for all of the non-selected rows. This voltage is large enough to turn ON the flash memory cells 14 even if their floating gates are storing charge. As a result, the bit line 20 for each column will be low if the cell 14 in that column of the selected row is not storing charge. Otherwise the bit line 20 remains high at VCC. The voltage on each bit line 20 is compared to a reference voltage by a respective sense amplifier (not shown). If the voltage on the bit line 20 is less than the reference voltage, the sense amplifier outputs a voltage corresponding to a “1” binary value of the read data bit. If the voltage on the bit line 20 is greater than the reference voltage, the sense amplifier outputs a voltage corresponding to a “0” binary value of the read data bit.
The select gate transistors 28 shown in FIG. 1 are NMOS transistors, which are normally fabricated in a p-well (not shown). When a selected row of flash memory cells 14 are to be erased, the word select line 30 for the selected row is coupled to ground, and the p-well is coupled to a positive voltage. The positive voltage is coupled through the PN junction formed by the p-well and the n-doped drain of the select gate transistors 28 to apply the positive voltage to the sources of the flash memory cells 14. The positive voltage then depletes charge from the floating gates in all of the cells 14, thereby erasing all of the memory cells 14 in the selected row. The flash memory cells 14 are normally erased on a block-by-block basis by grounding the word select lines 30 for all of the cells 14 in the block. Insofar as erasing the cells 14 removes charge from their floating gates, erasing the cells 14 effectively programs them to store logic “1” bit values.
When a selected row of cells 14 are to be programmed, a programming voltage is applied to the word select line 30 for the selected row, and a voltage sufficient to turn ON the remaining cells 14 is applied to the control gates of the remaining flash memory cells 14. Also, the first column select transistor 24 is turned ON and voltages corresponding to the data bits that are to be programmed are applied to the respective bit lines. If the voltage of a bit line 20 is at ground corresponding to a logic “0,” charge will be stored in the floating gate of the flash memory cell 14 in that column of the selected row. Otherwise, a voltage on the bit line 20 corresponding to a logic “1” prevents any charge from being stored on the floating gate. Programming is therefore performed on a row-by-row basis.
The storage capacity of a flash memory array can be increased by storing multiple bits of data in each flash memory cell 14. This can be accomplished by storing multiple levels of charge on the floating gate of each cell 14. These memory devices are commonly referred to as multi-bit or multi-level flash memory cells, known as “MLC memory cells.” In MLC cells, multiple bits of binary data corresponding to distinct threshold voltage levels defined over respective voltage ranges are stored within a single cell. Each distinct threshold voltage level corresponds to a respective combination of data bits. Specifically, the number N of bits requires 2N distinct threshold voltage levels. For example, for a flash memory cell to store 2 bits of data, 4 distinct threshold voltage levels corresponding to bit states 00, 01, 10, and 11 are needed. When reading the state of the memory cell, the threshold voltage level for which the memory cell 14 conducts current corresponds to a combination of bits representing data programmed into the cell. The two or more bits stored in each flash memory cell 14 can be adjacent bits in the same page of data. However, more frequently, one bit is treated as a bit in one page of data, and the other bit is treated as the corresponding bit in an adjacent page of data. The bit states assigned to respective charge levels are normally the same for all rows of memory cells in an array. The bit states assigned to the flash memory cells in the array are usually implemented in hardware and thus cannot be changed during operation of the flash memory device.
A multi-level flash memory cell is programmed by applying a programming voltage to the control gate and holding the drain to a constant voltage over a proper time period to store enough charge in the floating gate to move the threshold voltage Vt of the flash memory cell 14 to a desired level. This threshold voltage level Vt represents a bit state of the cell corresponding to the combination of data bits stored in the cell. As with programming single-level flash cells, programming of multi-level cells is performed on a row-by-row basis.
FIG. 2A illustrates the cell data map for a conventional one-bit-per-cell flash cell. As shown in FIG. 2A, two separate charge levels or ranges are defined within the overall flash cell threshold voltage Vt range. When reading from such a flash cell, all that is necessary is to determine whether the threshold voltage Vt is above or below the midpoint between the two levels. Voltages in one level are interpreted as a single binary bit (zero or one) while voltages in the other level are interpreted as the complementary binary bit (one or zero).
FIG. 2B, on the other hand, illustrates the cell data map for a multi-level flash memory cell capable of storing two bits. As can be seen in FIG. 2B, the data map defines four separate charge ranges or levels (Levels 0, 1, 2, and 3) within the range of the cell's overall maximum threshold voltage Vt. Each level is assigned a two-bit pair or bit-set 00, 01, 10, or 11. The bit sets are assigned for increasing levels of stored charge as 11, 01, 00, 10 so that only a single bit changes with each incremental increase in stored charge. The multiple bits stored in each row can be used as adjacent bits in a single page of memory. Alternatively, the multiple bits stored in each row can be used as corresponding bits in two different pages of memory. For example, the data bits X,Y stored in the first column can be used so that X is the first data bit of one page, and Y is the first data bit of an adjacent page.
As a result of the very large number of components in high capacity memory devices, including flash memory devices, it is not economically feasible to manufacture memory devices without any defects. If one allows memory devices to be manufactured with a few defective memory cells, the price of the memory device can be substantially reduced since much greater manufacturing yield can be attained. After manufacture, defective rows or columns of cells are detected during testing, and repair solutions incorporated into the memory devices themselves are used to perform repair these defects. In a NAND memory device, bit state errors in one or more memory cells in a row are normally corrected by conventional error checking and correcting (“ECC”) circuitry included in the memory device or a memory controller connected to the memory device. In the case of a larger number of errors in a row, such as those resulting from row-to-row shorts, the block containing the row is normally tagged as being defective, and a redundant block is substituted for the defective block. Column-to-column shorts are normally repaired by substituting a redundant column of memory cells for each defective column.
There is also a limit to the precision with which circuitry can store an analog value on the floating gate of a flash cell, particularly where multiple levels of charge must be stored. In particular, because of process variations, the flash cells across an entire array and even across a single row may not all behave identically. For these reasons, conventional circuitry for programming or erasing the flash cells typically perform these tasks in an iterative manner. Specifically, the circuitry applies a programming pulse having an appropriate duration and magnitude to a word select line 30. The pulse is applied to the control gate of each of the cells 14 to charge the floating gate to target levels corresponding to bit state values to which the cells are to be programmed. The cells are then interrogated to verify that the floating gate of each cell has been charged to that level. If the floating gate of a cell has been sufficiently charged, the voltage applied to the bit line for the cell is altered so that the floating gate will not be further charged if additional programming pulses are applied to the floating gate. The circuitry again applies a programming pulse to the control gate of each of the cells, and the cells are again verified. This process is repeated until the floating gates have been charged to the target levels. As can be appreciated, it can require a considerable period of time to program flash memory cells in this iterative manner. Additionally, each time the programming pulse is applied to a word select line 30, the pulse can inadvertently couple charge to floating gates of the programmed memory cells 14 in the corresponding row or an adjacent row. This problem is particularly acute for multi-level flash memory cells.
One approach to preventing an excessive number of programming pulses from being applied to a row is to simply consider the row to be properly programmed when the proper programming of less than all of the memory cells in the row have been verified. Using this technique, a “pseudo pass” condition is considered to exist even though one or more of the memory cells are programmed to erroneous bit states. These bit state errors can be corrected when the row is read using the conventional ECC techniques described above. However, these conventional ECC techniques are usually limited to repairing a relatively small number of data bit errors in each row. As a result of the large number of memory cells in the rows of conventional memory devices, the number of data bit errors existing after one or a few programming pulses have been applied to a row can exceed the number of data bit errors that can be corrected by ECC circuitry. To reduce the number of data bit errors to a level that can be corrected by the ECC circuitry, it is sometimes necessary to apply a long sequence of programming pulses to the word select line of a row of memory cells being programmed. For example, if the ECC circuitry is capable of correcting up to four data errors, programming pulses are applied until the number of programming errors has been reduced to four. As explained above, this can adversely affect the programmed state of previously programmed cells. Although this problem is described in the context of flash memory devices, it also exists in other types of non-volatile memory devices.
There is, therefore, a need for a flash memory device that allows a larger number of data bit errors to be corrected in each row of memory cells, thereby reducing the number of required programming pulses and/or allowing the data bit errors to be corrected by conventional ECC techniques.